Processing high volume scan test results for yield learning

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 293-298

  Crouch, Alfred L ^a   Burlison, Phil ^a   Ciplickas, Dennis ^b  

^a Inovys Corp

^b PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA ACQUISITION; FAILURE ANALYSIS; INFORMATION ANALYSIS; SYSTEMATIC ERRORS;

ELECTRIC TESTS; NANOMETER SCALE DEVICES; PHYSICAL CIRCUIT ELEMENTS;

LEARNING SYSTEMS;

EID: 34548127248     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.126     Document Type: Conference Paper

References (5)

1. A. J. Strojwas, "Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes", Keynote Address, Intl. Symposium on Semiconductor Manufacturing (ISSM), Tokyo, Japan, September 2006.
2. D. Ciplickas, S. Lee and A.J. Strojwas, "A New Paradigm for Evaluating IC Yield Loss", Solid State Technology, October 2001.
3. D. Ciplickas, A. Joshi, S. Lee and A. J. Strojwas, "Designing for High Product Yield", Semiconductor International, October 2002.
4. Alfred L. Crouch. Debugging and Diagnosing Scan Chains. Electronic Device Failure Analysis, vol. 7, no. 1, February 2005. pages 16-24.
5. Design & Test of Computers: Speed Test and Speed Binning for DSM Designs, vol. 20, no. 5, September-October 2003.