Effective and efficient test pattern generation for small delay defect

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 111-116

  Goel, Sandeep Kumar ^a   Devta Prasanna, Narendra ^a   Turakhia, Ritesh P ^b  

^a AGERE SYSTEMS   (United States)

^b LSI Corporation   (United States)

Author keywords

DPPM; Fault simulation; Small delay defects; Test quality; Timing aware ATPG; Transition fault pattern

Indexed keywords

DPPM; FAULT SIMULATION; SMALL DELAY DEFECTS; TEST QUALITY; TIMING-AWARE ATPG; TRANSITION FAULT PATTERN;

DYNAMIC RANDOM ACCESS STORAGE; PULSE POSITION MODULATION; TESTING; TIME MEASUREMENT;

DEFECTS;

EID: 70350353074     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.28     Document Type: Conference Paper

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