Not all delay tests are the same - SDQL model shows true-time

Proceedings of the Asian Test Symposium

Volumn 2006, Issue , 2006, Pages 147-152

  Uzzaman, Anis ^a   Tegethoff, Mick ^a   Bibo, Li ^a   Mc Cauley, Kevin ^a   Hamada, Shuji ^b   Sato, Yasuo ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; FAULT DETECTION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; STATISTICAL METHODS;

CIRCUIT TIMING; DELAY TESTS; FAULT TESTING; STATISTICAL DELAY QUALITY LEVEL (SDQL); STATISTICAL DELAY QUALITY MODEL (SDQM);

ELECTRONIC EQUIPMENT TESTING;

EID: 33947663571     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2006.261013     Document Type: Conference Paper

References (15)

1. A. Krstic and K.T. Cheng, "Delay fault testing for VLSI circuits," Kluwer Academic Publishers, Norwell, MA, 1998.
2. B.N. Dostie, "Design for at-speed test, diagnosis and measurement," Kluwer Academic Publishers, Boston, MA 1999
3. P. Gillis, et al, "Low Overhead Delay Testing of ASICs", Proceedings of the 2004 IEEE International Test Conference".
4. Y Sato, et al "Invisible Delay Quality-SDQM Model Lights Up What Could Not Be Seen", Proc IEEE International Test Conference 2005, pp
5. Y Sato, et al,"Evaluation of the Statistical Delay Quality Model ", Proc. ASP-DAC 2005, pp 305-310
6. E. S. Park, M. R. Mercer, and T. W. Williams, "Statistical delay fault coverage and defect level for delay faults," Proc. IEEE International Test Conference, pp. 160-167, 1988.
7. E. S. Park, B. Underwood, T. W. Williams, and M. R. Mercer, "Delay testing quality in timing-optimized designs," Proc. IEEE International Test Conference, pp. 168-176, 1991
8. P. Nigh and A. Gattiker, "Test method evaluation experiments & data," Proc. IEEE International Test Conference, pp. 454-463, 2000.
9. D. M. Wu and C. E. Radke, "Delay test effectiveness evaluation of LSSD-based VLSI logic circuits," Proc. ACM/IEEE Design Automation Conference, pp. 291-295, 1991.
10. N. N. Tendolkar, "Analysis of timing failures due to random AC defects in VLSI modules," Proc. ACM/IEEE Design Automation Conference, pp. 709-714, 1985.
11. V.S. Iyengar, B.K. Rosen, and J.A. Waicukauski, "On computing the sizes of detected delay faults," IEEE Trans. on Compt.-Aided Des. Integr. Circuits Syst., pp. 299-312, Mar. 1990.
12. D. S. Cleverley, "Product quality level monitoring and control for logic chips and modules," IBM J. Res. Develop, vol. 27, no. 1, January 1983.
13. L. C. Wang, A. Krstic, L. Lee, K. T. Cheng, M. R. Mercer, T. W. Williams, and M. S. Abadir, "Using logic models to predict the detection behavior of statistical timing defects," Proc. IEEE International Test Conference, pp. 1041-1050, 2003.
14. S. Mitra, E. Volkerink, E. McCluskey, and S. Eichenberger, "Delay defect screening using process monitor structures," Proc. IEEE VLSI Test Symposium, pp. 43-52, 2004.
15. V. Chickermane, B. Foutz, B. Keller, "Channel Masking Synthesis for Efficient On-Chip Test Compression", in Proc. 2004 IEEE Int. Test Conf., Oct. 2004. pp 452-461.