Silicon evaluation of longest path avoidance testing for small delay defects

Proceedings - International Test Conference

Volumn , Issue , 2007, Pages

  Turakhia, Ritesh ^a   Robert Daasch, W ^a   Ward, Mark ^b   Van Slyke, John ^b  

^a PORTLAND STATE UNIVERSITY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; INTEGRATED CIRCUIT LAYOUT; PRODUCTION; RELIABILITY THEORY;

PATH AVOIDANCE; PATH DELAY TESTING; PRODUCT QUALITY;

SEMICONDUCTING SILICON;

EID: 39749093842     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437564     Document Type: Conference Paper

References (24)