Reduction of number of paths to be tested in delay testing

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 5, 2000, Pages 477-485

  Li, Huawei ^a   Li, Zhongcheng ^a   Min, Yinghua ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; MATHEMATICAL MODELS; VLSI CIRCUITS;

PATH SENSITIZATION;

INTEGRATED CIRCUIT TESTING;

EID: 0034298335     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008368615938     Document Type: Article

References (15)

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