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Volumn , Issue , 2004, Pages 43-48

Delay defect screening using process monitor structures

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TESTING; PROCESS MONITORING; RING OSCILLATORS; STANDARD DEVIATION;

EID: 3142720622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2004.1299224     Document Type: Conference Paper
Times cited : (55)

References (14)
  • 1
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    • [Bassi 03] Bassi, A., A. Veggetti, L. Croce and A. Bogliolo, "Measuring the Effects of Process Variations on Circuit Performance by means of Digitally-Controllable Ring Oscillators," Proc. Intl. Conf. Microelectronic Test Structures, pp. 214-217, 2003.
    • (2003) Proc. Intl. Conf. Microelectronic Test Structures , pp. 214-217
    • Bassi, A.1    Veggetti, A.2    Croce, L.3    Bogliolo, A.4
  • 2
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    • Picosecond optical techniques offer a new dimension for microelectronics test
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    • [Jain 84] Jain, R.K., "Picosecond Optical Techniques Offer a New Dimension for Microelectronics Test," Test and Measurement World, pp. 40-53, June 1984.
    • (1984) Test and Measurement World , pp. 40-53
    • Jain, R.K.1
  • 4
    • 0142039803 scopus 로고    scopus 로고
    • Delay defect characteristics and testing strategies
    • [Kim 03]
    • [Kim 03] Kim, K.S., S. Mitra and P.G Ryan, "Delay Defect Characteristics and Testing Strategies," IEEE Design and Test of Computers, Vol. 20, No. 5, pp. 8-16, 2003.
    • (2003) IEEE Design and Test of Computers , vol.20 , Issue.5 , pp. 8-16
    • Kim, K.S.1    Mitra, S.2    Ryan, P.G.3
  • 5
    • 51449088512 scopus 로고    scopus 로고
    • Statistical post-processing at wafer sort - An alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies
    • [Madge 02]
    • [Madge 02] Madge, R., M. Rehani, K. Cota and W.R. Daasch, "Statistical Post-Processing at Wafer Sort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-Micron Technologies," Proc. IEEE VLSI Test Symp., pp. 69-74, 2002.
    • (2002) Proc. IEEE VLSI Test Symp. , pp. 69-74
    • Madge, R.1    Rehani, M.2    Cota, K.3    Daasch, W.R.4
  • 6
    • 0034482031 scopus 로고    scopus 로고
    • Stuck-at faults vs. actual defects
    • [McCluskey 00]
    • [McCluskey 00] McCluskey, E.J., and C.W. Tseng, "Stuck-at Faults vs. Actual Defects," Proc. Intl. Test Conf., pp. 336-343, 2000.
    • (2000) Proc. Intl. Test Conf. , pp. 336-343
    • McCluskey, E.J.1    Tseng, C.W.2
  • 7
    • 0030678746 scopus 로고    scopus 로고
    • Logic product speed evaluation and forecasting during the early phases of process technology development using ring oscillator data
    • [Milor 97]
    • [Milor 97] Milor, L, L. Yu and B. Liu, "Logic Product Speed Evaluation and Forecasting during the Early Phases of Process Technology Development using Ring Oscillator Data," Proc. Intl. Workshop Statistical Metrology, pp. 20-23, 1997.
    • (1997) Proc. Intl. Workshop Statistical Metrology , pp. 20-23
    • Milor, L.1    Yu, L.2    Liu, B.3
  • 8
    • 0024125123 scopus 로고
    • Statistical delay fault coverage and defect level for delay faults
    • [Park 88]
    • [Park 88] Park, E.S., M.R. Mercer, and T.W. Williams, "Statistical Delay Fault Coverage and Defect Level for Delay Faults," Proc. Int'l Test Conf., pp. 492-499, 1988.
    • (1988) Proc. Int'l Test Conf. , pp. 492-499
    • Park, E.S.1    Mercer, M.R.2    Williams, T.W.3
  • 9
    • 0142246911 scopus 로고    scopus 로고
    • An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit
    • [Qiu 03]
    • [Qiu 03] Qiu, W., and D.M.H. Walker, "An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit," Proc. Intl. Test Conf., pp. 592-601, 2003.
    • (2003) Proc. Intl. Test Conf. , pp. 592-601
    • Qiu, W.1    Walker, D.M.H.2
  • 10
  • 11
    • 0036444572 scopus 로고    scopus 로고
    • Scan-based transition fault testing implementation and low-cost test challenges
    • [Saxena 02]
    • [Saxena 02] Saxena, J., et al., "Scan-based Transition Fault Testing Implementation and Low-Cost Test Challenges," Proc. Intl. Test Conf., pp. 1120-1129, 2002.
    • (2002) Proc. Intl. Test Conf. , pp. 1120-1129
    • Saxena, J.1
  • 12
    • 0036443068 scopus 로고    scopus 로고
    • Finding a small set of longest testable paths that cover every gate
    • [Sharma 02]
    • [Sharma 02] Sharma, M., and J.H. Patel, "Finding a Small Set of Longest Testable Paths that Cover Every Gate," Proc. Intl. Test Conf., pp. 974-982, 2002.
    • (2002) Proc. Intl. Test Conf. , pp. 974-982
    • Sharma, M.1    Patel, J.H.2
  • 13
    • 0035684196 scopus 로고    scopus 로고
    • Multiple-output propagation transition fault test
    • [Tseng 01]
    • [Tseng 01] Tseng, C.W., and E.J. McCluskey, "Multiple-Output Propagation Transition Fault Test," Proc. Intl. Test Conf., pp. 358-366, 2001.
    • (2001) Proc. Intl. Test Conf. , pp. 358-366
    • Tseng, C.W.1    McCluskey, E.J.2
  • 14
    • 0142153750 scopus 로고    scopus 로고
    • Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die
    • [Yan 03]
    • [Yan 03] Yan, H., and A.D. Singh, "Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die," Proc. Intl. Test Conf., pp. 105-111, 2003.
    • (2003) Proc. Intl. Test Conf. , pp. 105-111
    • Yan, H.1    Singh, A.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.