Masking timing errors on speed-paths in logic circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 87-92

  Choudhury, Mihir R ^a   Mohanram, Kartik ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ERRORS; LOGIC CIRCUITS; LOGIC DESIGN; PROGRAM DEBUGGING; SPEED; TIMING CIRCUITS;

BENCHMARK CIRCUIT; CIRCUIT AGING; CRITICAL PATH DELAYS; DESIGN MARGINALITIES; NON-INTRUSIVE; RUN-TIME INFORMATION; SILICON DEBUG; TIMING ERRORS;

COMPUTER CIRCUITS;

EID: 70350053149     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090638     Document Type: Conference Paper

References (28)

1. S. Borkar, "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation," IEEE Micro, vol. 25, pp. 10-16, 2005.
2. D. Frank et al., "Design and CAD challenges in 45nm CMOS and beyond," in Proc. Intl. Conference Computer-aided Design, pp. 329-333, 2006.
3. D. K. Pradhan, ed., Fault-tolerant computing: Theory and techniques, vol. 1. Prentice-Hall, NJ, USA, 1986.
4. M. Gössel and S. Graf, Error detection circuits. McGraw-Hill Book Company, London, UK, 1993.
5. P. Franco et al., "On-line delay testing of digital circuits," in Proc. VLSI Test Symposium, pp. 167-173, 1994.
6. M. Favalli et al., "Sensing circuit for on-line detection of delay faults," IEEE Trans. VLSI Systems, vol. 4, pp. 130-133, 1996.
7. Y. Tsiatouhas et al., "A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs," in Proc. Intl. On-line Testing Symposium, pp. 12-16, 2003.
8. D. Ernst et al., "Razor: A low-power pipeline based on circuit-level timing speculation," in Proc. Intl. Symposium on Microarchitecture, pp. 7-18, 2003.
9. K. Bowman et al., "Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance," in Proc. Intl. Solid-state Circuits Conference, pp. 402-403,623, 2008.
10. M. Agarwal et al., "Circuit failure prediction and its application to transistor aging," in Proc. VLSI Test Symposium, vol. 32, pp. 277-286, 2007.
11. T. Austin et al., "DIVA: A reliable substrate for deep submicron microarchitecture design," in Proc. Intl. Symposium on Microarchitecture, pp. 196-207, 1999.
12. J. Srinivasan et al., "The case for lifetime reliability-aware microprocessors," in Proc. Intl. Symposium on Computer Architecture, pp. 276-287, 2004.
13. J. Blome et al., "Online timing analysis for wearout detection," in Workshop on Architectural Reliability, pp. 51-60, 2006.
14. J. Smolens et al., "Detecting emerging wearout faults," in Workshop on Silicon Errors in Logic - System Effects, pp. 276-287, 2007.
15. S. Kundu and S.M. Reddy, "On symmetric error correcting and all unidirectional error detecting codes," IEEE Trans. Computers, vol. 39, pp. 752-761, 1990.
16. N. K. Jha and S. Wang, "Design and synthesis of self-checking VLSI circuits," IEEE Trans. Computer-aided Design, vol. 2, pp. 878-887, 1993.
17. N. A. Touba and E. J. McCluskey, "Logic synthesis of multilevel circuits with concurrent error detection," IEEE Trans. Computer-aided Design, vol. 16, pp. 783-789, 1997.
18. A. Paschalis et al., "Concurrent delay testing in totally self-checking systems," in Journal of Electronic Testing: Theory and Applications, vol. 12, pp. 55-61, 1998.
19. S. Almukhaizim et al., "On the minimization of potential transient errors and SER in logic circuits using SPFD," in Proc. Intl. On-line Testing Symposium, pp. 123-128, 2008.
20. S. Krishnaswamy et al., "Enhancing design robustness with reliability-aware resynthesis and logic simulation," in Proc. Intl. Conference Computer-aided Design, pp. 149-154, 2007.
21. J. Tschanz et al., "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in Proc. Intl. Solid-state Circuits Conference, pp. 292-293,604, 2007.
22. Y.-S. Su et al., "An efficient mechanism for performance optimization of variable-latency designs," in Proc. Design Automation Conference, pp. 976-981, 2007.
23. A. Hopkins et al., "Debug support for complex systems on-chip: A review," in Proc. Computers and Digital Techniques, pp. 197-207, 2006.
24. M. Abramovici, "In-system silicon validation and debug," IEEE Design and Test of Computers, vol. 25, no. 3, pp. 216-223, 2008.
25. J.-S. Yang et al., "Expanding trace buffer observation window for in-system silicon debug through selective capture," in Proc. VLSI Test Symposium, pp. 345-351, 2008.
26. A. Saldanha et al., "Performance optimization using exact sensitization," in Proc. Design Automation Conference, pp. 425-429, 1994.
27. L. Benini et al., "Telescopic units: A new paradigm for performance optimization of vlsi designs," IEEE Trans. Computer-aided Design, vol. 17, pp. 220-232, 1998.
28. L. Benini et al., "Automatic synthesis of large telescopic units based on nearminimum timed supersetting," IEEE Trans. Computers, vol. 48, pp. 769-779, 1999.