An efficient mechanism for performance optimization of variable-latency designs

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 976-981

  Su, Yu Shih ^a   Wang, Da Chung ^a   Chang, Shih Chieh ^a   Marek Sadowska, Malgorzata ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Logic synthesis; Throughput optimization; Timing analysis

Indexed keywords

LATENCY DESIGNS; LOGIC SYNTHESIS; THROUGHPUT OPTIMIZATION; TIMING ANALYSIS;

LOGIC CIRCUITS; OPTIMIZATION; TELESCOPES; TIME DELAY; TIMING CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 34547294273     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375307     Document Type: Conference Paper

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