-
1
-
-
0031076832
-
Design Issues in Division and Other Floating-Point Operations
-
Feb.
-
S.F. Oberman and M.J. Flynn, "Design Issues in Division and Other Floating-Point Operations," IEEE Trans. Computers, vol. 46, no. 2, pp. 154-161, Feb. 1997.
-
(1997)
IEEE Trans. Computers
, vol.46
, Issue.2
, pp. 154-161
-
-
Oberman, S.F.1
Flynn, M.J.2
-
2
-
-
0032024306
-
Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs
-
Mar.
-
L. Benini, G. De Micheli, E. Macii, and M. Poncino, "Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 220-232, Mar. 1998.
-
(1998)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.17
, Issue.3
, pp. 220-232
-
-
Benini, L.1
De Micheli, G.2
Macii, E.3
Poncino, M.4
-
3
-
-
0031122218
-
Algebraic Decision Diagrams and Their Applications
-
R.I. Bahar, E.A. Frohm, C.M. Gaona, G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Algebraic Decision Diagrams and Their Applications," Formal Methods in System Design, vol. 10, pp. 171-206, 1997.
-
(1997)
Formal Methods in System Design
, vol.10
, pp. 171-206
-
-
Bahar, R.I.1
Frohm, E.A.2
Gaona, C.M.3
Hachtel, G.D.4
Macii, E.5
Pardo, A.6
Somenzi, F.7
-
4
-
-
33747079162
-
Symbolic Timing Analysis and Re-Synthesis for Low Power of Combinational Circuits Containing False Paths
-
Oct.
-
R.I. Bahar, H. Cho, G.D. Hachtel, E. Macii, F. Somenzi, "Symbolic Timing Analysis and Re-Synthesis for Low Power of Combinational Circuits Containing False Paths," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, pp. 1,101-1,115 Oct. 1997.
-
(1997)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.16
, Issue.10
-
-
Bahar, R.I.1
Cho, H.2
Hachtel, G.D.3
Macii, E.4
Somenzi, F.5
-
6
-
-
0002609165
-
A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran
-
Kyoto, Japan, June
-
F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. ISCAS-85: IEEE Int'l Symp. Circuits and Systems, pp. 785-794, Kyoto, Japan, June 1985.
-
(1985)
Proc. ISCAS-85: IEEE Int'l Symp. Circuits and Systems
, pp. 785-794
-
-
Brglez, F.1
Fujiwara, H.2
-
7
-
-
0024913805
-
Combinational Profiles of Sequential Benchmark Circuits
-
Portland, Ore., May
-
F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. ISCAS-89: IEEE Int'l Symp. Circuits and Systems, pp. 1,929-1,934, Portland, Ore., May 1989.
-
(1989)
Proc. ISCAS-89: IEEE Int'l Symp. Circuits and Systems
-
-
Brglez, F.1
Bryan, D.2
Kozminski, K.3
-
9
-
-
0022769976
-
Graph-Based Algorithms for Boolean Function Manipulation
-
Aug.
-
R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, vol. 35, no. 8, pp. 79-85, Aug. 1986.
-
(1986)
IEEE Trans. Computers
, vol.35
, Issue.8
, pp. 79-85
-
-
Bryant, R.1
-
10
-
-
0026913667
-
Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams
-
Sept.
-
R. Bryant, "Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams," ACM Computing Surveys, vol. 24, no. 3, pp. 293-318, Sept. 1992.
-
(1992)
ACM Computing Surveys
, vol.24
, Issue.3
, pp. 293-318
-
-
Bryant, R.1
-
11
-
-
0023012982
-
Timing Analysis Using Functional Analysis
-
Santa Clara, Calif., Nov.
-
D. Brand and V.S. Iyengar, "Timing Analysis Using Functional Analysis," Proc. ICCAD-86: Int'l Conf. Computer-Aided Design, pp. 126-129, Santa Clara, Calif., Nov. 1986.
-
(1986)
Proc. ICCAD-86: Int'l Conf. Computer-Aided Design
, pp. 126-129
-
-
Brand, D.1
Iyengar, V.S.2
-
12
-
-
0027544793
-
Path Sensitization in Critical Paths
-
Feb.
-
H.C. Chen and D.H.C. Du, "Path Sensitization in Critical Paths," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 196-207, Feb. 1993
-
(1993)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.2
, pp. 196-207
-
-
Chen, H.C.1
Du, D.H.C.2
-
13
-
-
0027849390
-
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms
-
Dec.
-
S. Devadas, K. Keutzer, and S. Malik, "Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1,913-1,923, Dec. 1993.
-
(1993)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.12
-
-
Devadas, S.1
Keutzer, K.2
Malik, S.3
-
14
-
-
0003101648
-
Sequential Circuits Design Using Synthesis and Optimization
-
Cambridge, Mass., Oct.
-
E.M. Sentovich, K.J. Singh, C.W. Moon, H. Savoj, R.K. Brayton, A. Sangiovanni-Vincentelli, "Sequential Circuits Design Using Synthesis and Optimization," Proc. ICCD-92: IEEE Int'l Conf. Computer Design, pp. 328-333, Cambridge, Mass., Oct. 1992.
-
(1992)
Proc. ICCD-92: IEEE Int'l Conf. Computer Design
, pp. 328-333
-
-
Sentovich, E.M.1
Singh, K.J.2
Moon, C.W.3
Savoj, H.4
Brayton, R.K.5
Sangiovanni-Vincentelli, A.6
-
15
-
-
0004000699
-
-
technical report, Dept. of Electrical and Computer Eng., Univ. of Colorado, Boulder, Apr.
-
F. Somenzi, CUDD: University of Colorado Decision Diagram Package, Release 2.1.2, technical report, Dept. of Electrical and Computer Eng., Univ. of Colorado, Boulder, Apr. 1997.
-
(1997)
CUDD: University of Colorado Decision Diagram Package, Release 2.1.2
-
-
Somenzi, F.1
-
16
-
-
0026107125
-
On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication
-
Feb.
-
R.E. Bryant, "On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication," IEEE Trans. Computers, vol. 40, no. 2, pp. 205-213, Feb. 1991.
-
(1991)
IEEE Trans. Computers
, vol.40
, Issue.2
, pp. 205-213
-
-
Bryant, R.E.1
|