Concurrent delay testing in totally self-checking systems

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 12, Issue 1-2, 1998, Pages 55-61

  Paschalis, Antonis ^a   Gizopoulos, Dimitris ^a   Gaitanis, Nikolaus ^a  

^a INSTITUTE OF INFORMATICS AND TELECOMMUNICATIONS   (Greece)

Author keywords

Concurrent on line detection; Duplication systems; Error indicators; Path delay faults; Totally self checking circuits

Indexed keywords

CODES (SYMBOLS); DETECTOR CIRCUITS; ERROR DETECTION; VLSI CIRCUITS;

CONCURRENT DELAY TESTING; PATH DELAY FAULTS; TOTALLY SELF CHECKING CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0032001949     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008213304310     Document Type: Article

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