메뉴 건너뛰기




Volumn , Issue , 2002, Pages 165-169

Active replication: Towards a truly SRAM-based FPGA on-line concurrent testing

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FAULT TREE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 70349346500     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2002.1030201     Document Type: Conference Paper
Times cited : (14)

References (18)
  • 1
    • 0031649068 scopus 로고    scopus 로고
    • Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
    • Jan
    • F. Hanchek, S. Dutt, "Methodologies for Tolerating Cell and Interconnect Faults in FPGAs", IEEE Trans. on Computers, Vol. 47, No. 1, pp. 15-33, Jan. 1998.
    • (1998) IEEE Trans. on Computers , vol.47 , Issue.1 , pp. 15-33
    • Hanchek, F.1    Dutt, S.2
  • 3
    • 0032293995 scopus 로고    scopus 로고
    • On-Line Fault Detection for Bus-Based Field Programmable Gate Arrays
    • Dec
    • N. R. Shnidman, H. W. Mangione-Smith, M. Potkonjak, "On-Line Fault Detection for Bus-Based Field Programmable Gate Arrays", IEEE Trans. on VLSI, Vol. 6, No. 4, pp. 656-666, Dec. 1998.
    • (1998) IEEE Trans. on VLSI , vol.6 , Issue.4 , pp. 656-666
    • Shnidman, N.R.1    Mangione-Smith, H.W.2    Potkonjak, M.3
  • 9
  • 10
    • 0033890073 scopus 로고    scopus 로고
    • An approach for detecting multiple faulty FPGA logic blocks
    • Jan
    • W. K. Huang, F. J. Meyer, F. Lombardi, "An approach for detecting multiple faulty FPGA logic blocks", IEEE Trans. on Computers, Vol. 49, No. 1, pp. 48-54, Jan. 2000.
    • (2000) IEEE Trans. on Computers , vol.49 , Issue.1 , pp. 48-54
    • Huang, W.K.1    Meyer, F.J.2    Lombardi, F.3
  • 11
    • 0031655580 scopus 로고    scopus 로고
    • Universal Fault Diagnosis for Look-up Table FPGAs
    • January-March
    • T. Inoue, S. Miyazaki, H. Fujiwara, "Universal Fault Diagnosis for Look-up Table FPGAs", IEEE Design and Test of Computers, Vol. 15, No 1, pp. 39-44, January-March 1998.
    • (1998) IEEE Design and Test of Computers , vol.15 , Issue.1 , pp. 39-44
    • Inoue, T.1    Miyazaki, S.2    Fujiwara, H.3
  • 12
    • 32144458848 scopus 로고    scopus 로고
    • RAM-Based FPGA's: A Test Approach for the Configurable Logic
    • February
    • M. Renovell, J. M. Portal, J. Figueras, Y. Zorian, "RAM-Based FPGA's: A Test Approach for the Configurable Logic", Proc. DATE Conf., pp. 82-88, February 1998.
    • (1998) Proc. DATE Conf. , pp. 82-88
    • Renovell, M.1    Portal, J.M.2    Figueras, J.3    Zorian, Y.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.