DRAFT: An on-line fault detection method for dynamic and partially reconfigurablefpgas

Proceedings - 7th International On-Line Testing Workshop, IOLTW 2001

Volumn 2001-January, Issue , 2001, Pages 34-36

  Gericota, Manuel G ^a   Alves, Gustavo R ^a   Silva, Miguel L ^b   Ferreira, Josk M ^b  

^a Department of Electrical Engineering   (United States)

^b UNIVERSITY OF PORTO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC MODELS; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE HARDWARE;

CONCURRENT RECONFIGURATION; FAULT-FREE OPERATIONS; IN-SYSTEM PROGRAMMING; ON-LINE FAULT DETECTION; PARTIAL DYNAMIC RECONFIGURATION; RECONFIGURABLE SYSTEMS; RECONFIGURATION PROCESS; SYSTEM OPERATION;

FAULT DETECTION;

EID: 10444289083     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/olt.2001.937814     Document Type: Conference Paper

References (6)

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2. Shnidman, N. R., Mangione-Smith, H., Potkonjak, M., "On-Line Fault Detection for Bus-Based Field Programmable Gate Arrays", IEEE Trans. on VLSI Systems, Vol. 6, No 4, pp. 656-666, December 1998.
3. IEEE Standard Test Access Port arid Boundan Scan Archirecture (IEEE Std 1149. 1). IEEE Standards Board, October 1993.
4. Abramovici, M., Stroud, M., Wijesuriya, S., Hamilton, C., Verma, V., "On-Line Testing and Diagnosis of FPGAs with Roving STARS", Proc. of the 5th IEEE International On-Line Testing Workshop, pp. 2-1, July 1999.
5. Gericota, M. G.; Alves, G. R., Ferreira, J. M., "Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test", 2nd IEEE Latin-American Test Workshop Digest of Papers, pp. 180-185, Feb. 2001.
6. Huang, W. K., Meyer, F. J., Chen, X., Lombardi, F., "Testing Configurable LUT-Based FPGA's", IEEE Trans. on VLSI Systems, Vol. 6, No 2, pp. 276-283, June 1998.