An approach for detecting multiple faulty FPGA logic blocks

IEEE Transactions on Computers

Volumn 49, Issue 1, 2000, Pages 48-54

  Huang, Wei Kang ^b   Meyer, Fred J ^a,c   Lombardi, Fabrizio ^a,c  

^a IEEE   (United States)

^b FUDAN UNIVERSITY   (China)

^c Northeastern University   (United States)

Author keywords

C testability; Fault tolerance; FPGA; Multiple faults; PLD

Indexed keywords

ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; TREES (MATHEMATICS);

BLOCK DETECTION; C-TESTABILITY; FAULT TOLERANCE; LOGIC BLOCKS; MULTIPLE FAULTS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033890073     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.822563     Document Type: Article

References (8)

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