Layout dependence modeling for 45-nm CMOS with stress-enhanced technique

IEEE Transactions on Electron Devices

Volumn 56, Issue 9, 2009, Pages 1991-1998

  Morifuji, Eiji ^a   Aikawa, Hisashi ^a   Yoshimura, Hisao ^a   Sakata, Akio ^a   Ohta, Masako ^a   Iwai, Masaaki ^a   Matsuoka, Fumitomo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

CMOS digital integrated circuits; CMOSFET logic devices; Integrated circuit layout; SPICE; Stress

Indexed keywords

CELL LIBRARY; CHANNEL DIRECTIONS; CHANNEL PROFILE; CMOS DIGITAL INTEGRATED CIRCUITS; CMOS LOGIC; CMOSFET LOGIC DEVICES; COMPACT MODEL; CONTACT POSITION; DEPENDENCE MODELING; DESIGN FLOWS; GEOMETRICAL PARAMETERS; MOSFETS; SATURATION CURRENT; SPACE EFFECTS; STRESS EFFECTS; STRESS LINER;

CELL MEMBRANES; CELLULAR RADIO SYSTEMS; CMOS INTEGRATED CIRCUITS; DIFFUSION; DIGITAL DEVICES; DIGITAL INTEGRATED CIRCUITS; END EFFECTORS; INTEGRATED CIRCUITS; LIBRARIES; LOGIC CIRCUITS; LOGIC DEVICES; SPICE;

INTEGRATED CIRCUIT LAYOUT;

EID: 69549084432     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2026121     Document Type: Article

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