Litho aware method for circuit timing/power analysis through process

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6521, Issue , 2007, Pages

  Fathy, R S ^a   Al Imam, M ^a   Diab, H ^a   Fakhry, M M ^a   Torres, J A ^a   Graupp, B ^a   Brunet, J M ^a   Bahnas, M S ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTOURS CONSIDERATIONS; PROCESS VARIATIONS;

COMPUTER SIMULATION; LITHOGRAPHY; NANOTECHNOLOGY; WAFER BONDING;

INTEGRATED CIRCUIT LAYOUT;

EID: 35048820988     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.711723     Document Type: Conference Paper

References (6)

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2. P. Gupta, A.B. Kahng, et. al. "Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation" Proc. SPIE Int. Soc. Opt. Eng. 6156, 91 (2006).
3. W.J. Poppe, L. Capodieci, et.al "From poly line to transistor: building BSIM models for non-rectangular transistor". Proc. SPIE Int. Soc. Opt. Eng., 6156, 235 (2006).
4. W.J. Poppe, L. Capodieci, et. al "Platform for collaborative DFM". Proc. SPIE Int. Soc. Opt. Eng 6156, 124 (2006).
5. J. A. Torres, C. Neil Berglund, "Integrated circuit DFM framework for deep sub-wavelength processes" Proc. SPIE Int. Soc. Opt. Eng. 5756, 39 (2005).
6. J. A. Torres, F.G. Pikus. "Unified Process-Aware System for Circuit Layout Verification". Proc. SPIE Int. Soc. Opt. Eng. Submitted.