A low-power digital DLL-based clock generator in open-loop mode

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 7, 2009, Pages 1907-1913

  Mesgarzadeh, Behzad ^a   Alvandpour, Atila ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

DLL dithering; DLL based clock generator; Frequency multiplier; Low power; Multiphase clock generator

Indexed keywords

DLL DITHERING; DLL-BASED CLOCK GENERATOR; FREQUENCY MULTIPLIER; LOW POWER; MULTIPHASE CLOCK GENERATOR;

ERROR COMPENSATION; FREQUENCY MULTIPLYING CIRCUITS; JITTER;

ELECTRIC CLOCKS;

EID: 67651171553     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2020229     Document Type: Article

References (14)

1. T. Fischer et al., "A 90-nm variable frequency clock system for a power-managed Itanium architecture processor," IEEE J. Solid-State Circuits, vol. 41, pp. 218-228, Jan. 2006.
2. S. Desai, P. Trivedi, and V. V. Kanael, "A dual-supply 0.2-to-4 GHz PLL clock multiplier in a 65 nm dual-oxide CMOS process," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 308-309.
3. B. Kim, T. Weigandt, and P. Gray, "PLL/DLL system noise analysis for low jitter clock synthesizer design," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1994, pp. 31-38.
4. R. Farjad-Rad, W. Dally, H. T. Ng, R. Senthinathan, M. J. E. Lee, R. Rathi, and J. Poulton, "A low-power multiplier DLL for low-jitter multigigahertz clock generation in highly integrated digital chips," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804-1812, Dec. 2002.
5. C. Kim, I.-C. Hwang, and S.-M. Kang, "A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1414-1420, Nov. 2002.
6. J.-H. Kim et al., "A CMOS DLL-based 120 MHz to 1.8 GHz clock generator for dynamic frequency scaling," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 516-517.
7. B. M. Helal, M. Z. Straayer, G. -Y. Wei, and M. H. Perrott, "A low-jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correction," in Symp. VLSI Circuits Dig. Tech. Papers, 2007, pp. 166-167.
8. Q. Du, J. Zhuang, and T. Kwasniewski, "A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1205-1209, Nov. 2006.
9. A. Alvandpour, R. K. Krishnamurthy, D. Eckerbert, S. Apperson, B. Bloechel, and S. Borkar, "A 3.5-GHz 32 mW 150 nm multiphase clock generator for high-performance microprocessors," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 112-113.
10. C.-C. Chung and C.-Y. Lee, "A new DLL-based approach for all-digital multiphase clock generation," J. Solid-State Circuits, vol. 39, no. 3, pp. 469-475, Mai-. 2004. [11] Y.-S. Kim, S. J. Park, Y.-S. Kim, D.-B. Jang, S.-W. Jeong, H.-J. Park, and J.-Y. Sim, "A 40-to-800 MHz locking multiphase DLL," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 306-307.
11. X. Maillard, F. Devisch, and M. Kuijk, "A 900 Mb/s CMOS data recovery DLL using half-frequency clock," J. Solid-State Circuits, vol. 37, no. 6, pp. 711-715, Jun. 2002.
12. H. H. Chang, R. J. Yang, and S. I. Liu, "Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 12, pp. 2356-2364, Dec. 2004. [14] Y. Moon and D. Shim, "A multiphase delay-locked loop for 0.125-2 Gbps 0.18 /μm CMOS transmitter," in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 35-36.
13. G. Hinton et al., "A 0.18-/μm CMOS IA-32 processor with a 4-GHz integer execution unit," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1617-1627, Nov. 2001.
14. D. E. Calbaza and Y. Savaria, "A direct digital period synthesis circuit," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1039-1045, Aug. 2002.