A direct digital period synthesis circuit

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 8, 2002, Pages 1039-1045

  Calbaza, Dorin Emil ^a,b   Savaria, Yvon ^a,c  

^a IEEE   (Canada)

^b Gennum Corporation   (Canada)

^c ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Direct digital synthesis; DLL based frequency multipliers; Frequency synthesis; Phase accumulators

Indexed keywords

DELAY LOCKED LOOP; DIRECT DIGITAL PERIOD SYNTHESIS CIRCUIT; PEAK-TO-PEAK JITTER;

CMOS INTEGRATED CIRCUITS; ELECTRIC FREQUENCY CONTROL; FREQUENCIES; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; TABLE LOOKUP;

ELECTRIC NETWORK SYNTHESIS;

EID: 0036683873     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.800923     Document Type: Article

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