A CMOS DLL-based 120MHz to 1.8GHz clock generator for dynamic frequency scaling

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Kim, Jin Han ^a   Kwak, Young Ho ^a   Yoon, Seok Ryung ^a   Kim, Moo Young ^a   Kim, Soo Won ^a   Kim, Chulwoo ^a  

^a Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144451016     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. G. Chien et al., "A 900MHz Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications," ISSCC Dig. Tech. Papers, pp. 202-203, Feb., 2000.
2. D. Foley et al., "CMOS DLL-Based 2V 3.2ps Jitter 1GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE J. Solid-State Circuits, pp. 417-423, Mar., 2001.
3. R. Farjad-rad et al., "A 0.2-2GHz 12mW Multiplying DLL for Low-Jitter Clock Synthesis in Highly-Integrated Data Communication Chips," ISSCC Dig. Tech. Papers, pp. 76-77, Feb., 2002.
4. C. Kim et al., "Low-Power Small-Area ± 7.28ps Jitter 1GHz DLL-based Clock Generator," ISSCC Dig. Tech. Papers, pp. 142-143, Feb., 2002.