A dual-supply 0.2-to-4GHz PLL clock multiplier in a 65nm dual-oxide CMOS process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 308-310

  Desai, Shaishav ^a   Trivedi, Pradeep ^a   Von Kanael, Vincent ^a  

^a PA Semi   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; JITTER; NATURAL FREQUENCIES; PHASE LOCKED LOOPS;

DUAL-OXIDE DEVICES; OUTPUT FREQUENCIES;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 34548855023     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373417     Document Type: Conference Paper

References (5)

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4. H. Chang and J. Wu, "A 723- MHz 17.2-mW CMOS Programmable Counter," IEEE J. Solid-State Circuits, pp. 1572-1575, Oct., 1998.
5. P. Larsson, "High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler," IEEE J. Solid-State Circuits, pp. 744-748, May, 1996.