A 900-Mb/s CMOS data recovery DLL using half-frequency clock

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 6, 2002, Pages 711-715

  Maillard, Xavier ^b   Devisch, Frédéric ^b   Kuijk, Maarten ^a,b  

^a IEEE

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

Data recovery; Delay locked loop; High speed CMOS; Phase detector

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CORRELATION DETECTORS; DATA COMMUNICATION SYSTEMS; ELECTRIC DELAY LINES; INTEGRATED CIRCUIT MANUFACTURE; JITTER; SYNCHRONIZATION;

DATA RECOVERY; DELAY-LOCKED LOOPS; HALF-FREQUENCY CLOCK; HIGH-SPEED CMOS; PHASE DETECTOR;

DELAY CIRCUITS;

EID: 0036612162     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.1004575     Document Type: Article

References (12)

1. Clock/data recovery PLL using half-frequency clock
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11. Low-jitter process-independent DLL and PLL based on self-biased techniques
12. A CMOS clock recovery circuit for 2.5-Gbit/s NRZ data