A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 11, 2006, Pages 1205-1209

  Du, Qingjin ^a   Zhuang, Jingcheng ^a   Kwasniewski, Tad ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

Delay locked loop (DLL); frequency multiplier; in lock erroi; Phase noise; phase locked loon (PLL); spurious power level

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; FREQUENCIES; FREQUENCY MULTIPLYING CIRCUITS; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS; TIMING JITTER;

DELAY LOCKED LOOP (DLL); FREQUENCY MULTIPLIER; IN-LOCK ERROR; PHASE NOISE; SPURIOUS POWER LEVEL;

PHASE LOCKED LOOPS;

EID: 34547559170     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.883103     Document Type: Article

References (7)

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