Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 12, 2004, Pages 2356-2364

  Chang, Hsiang Hui ^a   Yang, Rong Jyi ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock and data recovery circuit (CDR); Delay locked loop (DLL); Multirate; Phase locked loop (PLL)

Indexed keywords

BIT ERROR RATE; DELAY CIRCUITS; DETECTOR CIRCUITS; INTERCONNECTION NETWORKS; JITTER; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS;

CLOCK CIRCUITS; DATA RECOVERY CIRCUIT; DELAY LOCKED LOOP (DLL); RATE DETECTION CIRCUITS;

INTEGRATED CIRCUITS;

EID: 10944263801     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.838147     Document Type: Article

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