A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 166-167

  Helal, Belal M ^a   Straayer, Matthew Z ^a   Wei, Gu Yeon ^b   Perrott, Michael H ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

Correlation; Delay offset; Deterministic jitter; MDLL; Noise shaping; Reference spur; Scrambling; TDC

Indexed keywords

DELAY OFFSET; DETERMINISTIC JITTER; NOISE SHAPING; REFERENCE SPUR;

JITTER; RANDOM PROCESSES; SOFTWARE PROTOTYPING;

ANALOG TO DIGITAL CONVERSION;

EID: 39749105449     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342700     Document Type: Conference Paper

References (5)