A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Alvandpour, Atila ^a   Krishnamurthy, Ram K ^a   Eckerbert, Daniel ^b   Apperson, Stuart ^a   Bloechel, Bradley ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

^b CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ELECTRIC DELAY LINES; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; JITTER; LEAKAGE CURRENTS;

CLOCK FREQUENCIES; HIGH PERFORMANCE MICROPROCESSORS; MULTIPHASE CLOCK GENERATOR; POWER CONSUMPTION; PROGRAMMABLE DELAY LINES;

MICROPROCESSOR CHIPS;

EID: 0038306568     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. N. Kurd et. al., "A multigigahertz clocking scheme for the Pentium® 4 microprocessor," IEEE J. Solid-State Circuits, vol. 36, pp. 1647-1653, Nov. 2001.
3. S. Rusu et. al., "Clock generation and distribution for the first IA-64 microprocessor," in ISSCC, Dig. Tech. Papers, Feb. 2000, pp. 176-177.
4. J. Lee et. al., "Digitally-controlled DLL and I/O circuits for 500Mb/s/pin X16 DDR SDRAM," in ISSCC, Dig. Tech. Papers. Feb. 2001, pp.68-69.
5. G. Dehng et. al. "Clock-deskew buffer using a SAR-controlled delay-looked loop," IEEE J. Solid-State Circuits, vol. 35, pp. 1128-1136, August 2000.
6. K. Minami et al., "A 1GHz portable digital delay-locked loop with infinite phase capture ranges," in ISSCC, Dig. Tech. Papers, Feb. 2000, pp.350-351.
7. B. Garlepp et al., "A portable digital DLL for high-speed CMOS interface circuits," IEEE J. Solid-State Circuits, vol. 34, pp. 632-644, May 1999.