A new DLL-based approach for all-digital multiphase clock generation

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 3, 2004, Pages 469-475

  Chung, Ching Che ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Delay locked loops (DLLs); Digitally controlled delay line (DCDL); Multiphase clock generation; Phase synchronization

Indexed keywords

DESIGN FOR TESTABILITY; DIGITAL CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC NETWORK SYNTHESIS; FREQUENCY CONVERTERS; PHASE LOCKED LOOPS; TIMING CIRCUITS;

DELAY LOCKED LOOPS; DIGITAL MULTIPHASE CLOCK GENERATION; PHASE SYNCHRONIZATION; TIME TO DIGITAL CONVERTER;

DELAY CIRCUITS;

EID: 1542500851     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.822890     Document Type: Article

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