Vertical silicon-nanowire formation and gate-all-around MOSFET

IEEE Electron Device Letters

Volumn 29, Issue 7, 2008, Pages 791-794

  Yang, B ^a   Buddharaju, K D ^a   Teo, S H G ^a   Singh, N ^a   Lo, G Q ^a   Kwong, D L ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

CMOS technology; MOSFET; Si nanowire; Vertical

Indexed keywords

ASPECT RATIO; ELECTRIC WIRE; LITHOGRAPHY; MOS DEVICES; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOWIRES; NONMETALS; OPTICAL DESIGN; PHOTORESISTS; SILICON;

AND GATES; BULK SILICON; CMOS COMPATIBLE; DRIVE CURRENTS; DRY-ETCH; GA TE LENGTHS; GATE ALL AROUND (GAA); HIGH ASPECT RATIO (HAR); SACRIFICIAL OXIDE; SILICON NANOWIRE TRANSISTORS; SILICON-NANOWIRE; SURROUNDING GATE (SG); TRANSISTOR CHARACTERISTICS;

SILICON WAFERS;

EID: 47349086241     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2000617     Document Type: Article

References (22)

1. J. P. Colinge, M. H. Gao, A. R. Rodriguez, H. Maes, and C. Claeys, "Silicon-on-insulator: Gate-all-around device," in IEDM Tech. Dig. 1990, pp. 595-598.
2. S. Monfray, T. Skotniki, Y. Morand, S. Descombes, P. Coronel, P. Mazoyer, S. Harrison, P. Ribot, A. Talbot, D. Dutartre, M. Haond, R. Palla, Y. Le Friec, F. Leverd, M. E. Nier, C. Vizioz, and D. Louis, "50 nm-gate all around (GAA)-silicon on nothing (SON)-devices: A simple way to co-integration of GAA transistors with bulk MOSFET process," in VLSI Symp. Tech. Dig., 2002, pp. 108-109.
3. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
4. B. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003.
5. W. W. Fang, N. Singh, L. K. Bera, H. S. Nguyen, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Vertically stacked SiGe nanowire array channel CMOS transistors," IEEE Electron Device Lett., vol. 28, no. 3, pp. 211-213, Mar. 2007.
6. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May 2006.
7. J. Moers, "Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface," Appl. Phys., vol. A87, no. 3, pp. 531-537, Jun. 2007.
8. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, "High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs," in IEDM Tech. Dig., 1988, pp. 222-225.
9. K. Sunouchi, H. Takato, N. Okabe, T. Yamada, T. Ozaki, S. Inoue, K. Hashimoto, K. Hieda, A. Nitayama, F. Horiguchi, and F. Masuoka, "A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs," in IEDM Tech. Dig., 1989, pp. 23-26.
10. H. Sakuraba, K. Kinoshita, T. Tanigami, T. Yokoyama, S. Horii, M. Saitoh, K. Sakiyama, T. Endoh, and F. Masuoka, "New three-dimensional high-density stacked-surrounding gate transistor (S-SGT) flash memory architecture using self-aligned interconnection fabrication technology without photolithography process for tera-bits and beyond," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 2217-2219, Apr. 2004.
11. J. Sarkar, S. Dey, D. Shahrjerdi, and S. K. Banerjee, "Vertical flash memory cell with nanocrystal floating gate for ultradense integration and good retention," IEEE Electron Device Lett., vol. 28, no. 5, pp. 449-451, May 2007.
12. S. K. Jayanarayanan, S. Dey, J. P. Donnelly, and S. K. Banerjee, "A novel 50 nm vertical MOSFET with a dielectric pocket," Solid State Electron., vol. 50, no. 5, pp. 897-900, May 2006.
13. K. Endo, S. Noda, M. Masahara, T. Kubota, T. Ozaki, S. Samukawa, Y. X. Liu, K. Ishii, Y. Ishikawa, E. Sugimata, T. Matsukawa, H. Takashima, H. Yamauchi, and E. Suzuki, "Fabrication of a vertical-channel double-gate metal-oxide-semiconductor field-effect transistor using a neutral beam etching," Jpn. J. Appl. Phys., vol. 45, no. 10, pp. L279-L281, 2006.
14. M. Masahara, T. Matsukawa, H. Tanoue, K. Ishii, Y. X. Liu, K. Sakamoto, S. Kanemaru, and E. Suzuki, "Novel process for vertical double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET) fabrication," Jpn. J. Appl. Phys., vol. 42, no. 6B, pp. 4138-4141, Jun. 2003.
15. Y. Wu and P. Yang, "Germanium nanowire growth via simple vapor transport," Chem. Mater., vol. 12, no. 3, pp. 605-607, 2000.
16. X. Duan and C. M. Lieber, "General synthesis of compound semiconductor nanowires," Adv. Mater., vol. 12, no. 4, pp. 298-302, Feb. 2000.
17. Y. Huang and C. M. Lieber, "Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires," Pure Appl. Chem., vol. 76, no. 12, pp. 2051-2068, Dec. 2004.
18. M. Law, J. Goldberger, and P. Yang, "Semiconductor nanowires and nanotubes," Annu. Rev. Mater. Res., vol. 34, pp. 83-122, Aug. 2004.
19. G. Li, N. Xi, H. Chen, A. Saeed, and M. Yu, "Assembly of nanostructure using AFM based nanomanipulation system," in Proc. IEEE Int. Conf. Robot. Autom., 2004, vol. 1, pp. 428-433.
20. D. B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, "Two-dimensional thermal oxidation of silicon - I. Experiments," IEEE Trans. Electron Devices, vol. ED-34, no. 5, pp. 1008-1017, May 1987.
21. D. B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, "Two-dimensional thermal oxidation of silicon - II. Modeling stress effects in wet oxides," IEEE Trans. Electron Devices, vol. 35, no. 1, pp. 25-37, Jan. 1988.
22. C. P. Auth and J. D. Plummer, "Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFETs," IEEE Electron Device Lett., vol. 18, no. 2, pp. 74-76, Feb. 1997.