Dynamic simulation of void nucleation during electromigration in narrow integrated circuit interconnects

Journal of Applied Physics

Volumn 105, Issue 1, 2009, Pages

  Li, Wei ^a,b   Tan, Cher Ming ^b   Raghavan, Nagarajan ^c  

^a SYSTEMS ON SILICON MANUFACTURING CO PTE LTD   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT INTERCONNECTS; CONDUCTION PATHS; DAMAGE MECHANISM; DYNAMIC SIMULATION; FAILURE MECHANISM; INTEGRATED CIRCUIT INTERCONNECTIONS; INTERCONNECT TEST STRUCTURES; MEDIAN TIME TO FAILURES; MODELING CONCEPTS; MONTE CARLO SIMULATION; PHYSICS-BASED; SIMULATION METHODOLOGY; SUBMICROMETER; TIME TO FAILURE; VOID NUCLEATION; VOID SIZE;

ELECTROMIGRATION; MONTE CARLO METHODS; NUCLEATION; SIMULATORS;

INTEGRATED CIRCUITS;

EID: 67649830189     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3040159     Document Type: Article

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