Uncriticality-directed scheduling for tackling variation and power challenges

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 820-825

  Sato, Toshinori ^a,c   Watanabe, Shingo ^b,d  

^a FUKUOKA UNIVERSITY   (Japan)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^c KYUSHU UNIVERSITY   (Japan)

^d FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Low power; Microarchitecture; Variability resilience

Indexed keywords

CIRCUIT DELAYS; CONFIGURABLE; INSTRUCTION SCHEDULING; LATENCY TECHNIQUES; LOW POWER; MICROARCHITECTURE; MICROPROCESSOR DESIGNS; PARAMETER VARIATION; PERFORMANCE DEGRADATION; POWER CONSUMPTION; POWER REDUCTIONS; PROCESSOR PERFORMANCE; SCHEDULING TECHNIQUES; SEMICONDUCTOR TECHNOLOGY; SUPPLY VOLTAGES; VARIABILITY RESILIENCE;

ENERGY EFFICIENCY; EVAPORATIVE COOLING SYSTEMS; SEMICONDUCTOR DEVICE MANUFACTURE;

SCHEDULING;

EID: 67649648235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810398     Document Type: Conference Paper

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