Instruction scheduling for variation-originated variable latencies

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 361-364

  Sato, Toshinori ^a   Watanabe, Shingo ^b  

^a KYUSHU UNIVERSITY   (Japan)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAYS; CONVENTIONAL SCHEDULING; ELECTRONIC DESIGNS; INSTRUCTION SCHEDULING; INTERNATIONAL SYMPOSIUM; PARAMETER VARIATIONS; PERFORMANCE DEGRADATION; PROCESSOR PERFORMANCE; SEMICONDUCTOR TECHNOLOGIES;

ADDERS; ELECTRONICS ENGINEERING; SEMICONDUCTOR DEVICE MANUFACTURE; SULFATE MINERALS;

SCHEDULING;

EID: 49749121161     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479757     Document Type: Conference Paper

References (11)

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