Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 195-200

  Chen, Yiran ^a   Li, Hai ^a   Li, Jing ^b   Koh, Cheng Kok ^b  

^a SEAGATE TECHNOLOGY   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Negative bias temperature instability (NBTI); Variable latency adder (VL adder)

Indexed keywords

ARITHMETIC CIRCUIT DESIGN; PMOS TRANSISTORS; VARIABLE-LATENCY ADDER (VL-ADDER);

COSTS; DATA ACQUISITION; DIGITAL ARITHMETIC; ELECTRIC POTENTIAL; RELIABILITY; TRANSISTORS;

ELECTRIC NETWORK ANALYSIS;

EID: 36949004074     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283822     Document Type: Conference Paper

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