메뉴 건너뛰기




Volumn , Issue , 2008, Pages 83-88

AMPLE: An adaptive multi-performance processor for low-energy embedded applications

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE PROCESSING; BUFFER STORAGE; CACHE MEMORY; CONSERVATION; DATA STORAGE EQUIPMENT; ENERGY EFFICIENCY; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS;

EID: 52349121541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SASP.2008.4570790     Document Type: Conference Paper
Times cited : (18)

References (14)
  • 1
    • 27144556964 scopus 로고    scopus 로고
    • Intra-task voltage scheduling on DVS-enabled hard real-time systems
    • Oct
    • D. Shin and J. Kim, "Intra-task voltage scheduling on DVS-enabled hard real-time systems", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.24, Issue 10, pp. 1530-1549. Oct. 2005
    • (2005) IEEE Trans. on CAD of Integrated Circuits and Systems , vol.24 , Issue.10 , pp. 1530-1549
    • Shin, D.1    Kim, J.2
  • 7
    • 0032688679 scopus 로고    scopus 로고
    • Power Conscious Fixed Priority Scheduling for a Variable Voltage Processor
    • June
    • Y. Shin and K. Choi, "Power Conscious Fixed Priority Scheduling for a Variable Voltage Processor," in Proc. of Design Automation Conference, pp. 134-139, June, 1999.
    • (1999) Proc. of Design Automation Conference , pp. 134-139
    • Shin, Y.1    Choi, K.2
  • 9
    • 0033699538 scopus 로고    scopus 로고
    • Run-time Voltage Hopping for Low-power Real-time Systems
    • June
    • S. Lee, and T. Sakurai, "Run-time Voltage Hopping for Low-power Real-time Systems," in Proc. of Design Automation Conference, pp. 806-809, June, 2000.
    • (2000) Proc. of Design Automation Conference , pp. 806-809
    • Lee, S.1    Sakurai, T.2
  • 12
    • 77951449103 scopus 로고    scopus 로고
    • Toshiba Corp
    • Toshiba Corp., "MeP Core (MeP-c4) User's Manual," http://www.semicon.toshiba.co.jp/eng/product/micro/
    • MeP Core (MeP-c4) User's Manual
  • 14
    • 0036917242 scopus 로고    scopus 로고
    • Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads
    • Nov
    • S. M. Martin, K. Flautner, T. Mudge and D. Blaauw, "Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads," in Proc. of International Conference on Computer Aided Design, pp.721-725, Nov., 2002.
    • (2002) Proc. of International Conference on Computer Aided Design , pp. 721-725
    • Martin, S.M.1    Flautner, K.2    Mudge, T.3    Blaauw, D.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.