Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture

ANCS'07 - Proceedings of the 2007 ACM Symposium on Architecture for Networking and Communications

Volumn , Issue , 2007, Pages 47-56

  Kodi, Avinash ^a   Sarathy, Ashwini ^b   Louri, Ahmed ^b  

^a OHIO UNIVERSITY   (United States)

^b University of Arizona   (United States)

Author keywords

low power design; network on chip

Indexed keywords

ADAPTIVE CHANNEL BUFFERS; ADAPTIVE COMMUNICATIONS; AREA EFFICIENT; AREA OVERHEAD; BUFFER ALLOCATION; DEEP SUB-MICRON; DYNAMIC BUFFER ALLOCATION; LOW POWER; LOW-POWER DESIGN; NETWORK ON CHIP; NETWORK POWER; NETWORK-ON-CHIP ARCHITECTURES; NOC ARCHITECTURES; POWER CONSUMPTION; ROUTER BUFFER; SCALABLE SOLUTION; SIMULATION RESULT; STATIC AND DYNAMIC; TORUS NETWORKS; TRAFFIC PATTERN; VLSI DESIGN; WIRE DELAYS;

CIVIL AVIATION; COMMUNICATION; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DESIGN; DROPS; ELECTRIC NETWORK TOPOLOGY; VLSI CIRCUITS;

ROUTERS;

EID: 56849097592     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1323548.1323561     Document Type: Conference Paper

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