SEU hardened clock regeneration circuits

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 806-813

  Dash, Rajballav ^a   Garg, Rajesh ^a   Khatri, Sunil P ^a   Choi, Gwan ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Clock Regeneration; Single Event Upset (SEU); Soft Errors

Indexed keywords

CHIP-LEVEL; CLOCK NETWORK; CLOCK-JITTER; DEEP SUB-MICRON; DEVICE-SCALING; NEW DESIGN; OPERATING FREQUENCY; RADIATION PARTICLES; RADIATION-INDUCED; SINGLE EVENT UPSET (SEU); SINGLE EVENT UPSETS; SOFT ERROR RATE; SOFT ERRORS; SUPPLY VOLTAGES; VLSI SYSTEM;

DESIGN; ELECTRIC CLOCKS; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; HARDENING; JITTER; MICROPROCESSOR CHIPS; RADIATION; REGENERATORS; STATIC RANDOM ACCESS STORAGE; URANIUM POWDER METALLURGY; VLSI CIRCUITS;

RADIATION HARDENING;

EID: 67649640004     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810396     Document Type: Conference Paper

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