A Proposed SEU Tolerant Dynamic Random Access Memory (DRAM) Cell

IEEE Transactions on Nuclear Science

Volumn 41, Issue 6, 1994, Pages 2035-2042

  Agrawal, Ghasi R ^a   Massengill, Lloyd W ^a   Gulati, Kush ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CAPACITORS; CELLULAR ARRAYS; COMPUTER SIMULATION; ELECTROMAGNETIC SHIELDING; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; RADIATION EFFECTS; SEMICONDUCTOR DIODES; TRANSISTORS;

DYNAMIC RANDOM ACCESS MEMORY; SINGLE EVENT CELL ERRORS; SOFTWARE PACKAGE SPICE;

RANDOM ACCESS STORAGE;

EID: 0028714164     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.340539     Document Type: Article

References (12)

1. Cheon et al., “Trench DRAM Cell with Vertical Transistor,” US Patent No. 5252845, Oct 1993.
2. N. C. C. Lu, “Advanced Cell Structures for Dynamic RAMs,” IEEE Circuits and Devices Magazine, pp 370–378, 1989.
3. Takeshi et al., “A 17-ns 4-Mb CMOS DRAM,” IEEE JSSC, Vol. 2, pp 1538–1542 Nov. 1991.
4. Mikio et al., “Cell-Plate Line Connecting Complementary Bit line Architecture for Battery-Operating DRAM’s,” IEEE BSC, Vol. 27, No 4, pp 597–601, April 1992.
5. Richard J. McPartland, “Circuit Simulations of Alpha-Particle-Induced Induced Soft Errors in MOS Dynamic RAM’s,” IEEE JSSC, Vol. Sc-16, pp.31-34, No. 1, Feb. 1981.
6. Rajeevakurnar et al., “A New Failure Mode of Radiation Induced Soft Errors in Dynamic Memories,” IEEE Electron Device Letters, Vol. 9, No. 12, pp 644–646, Dec. 1988.
7. T. C. May, and M. H. Woods, “ Alpha-Particle-Induced Soft Errors in Dynamic Memories,” IEEE Iran. on Electron Devices, Vol. ED-26, No. 1, pp 2–9, January 1979.
8. S. K. Banerjee, “Two-Transistor DRAM Cell with High Alpha Particle Immunity,” US Patent No. 4864374, Sep. 1989.
9. Gonzalez, “Dynamic Random Access Memory Cell having Stacked Trench Capacitor that is Resistant to Alpha-Particle Generated Soft Errors, and Method of Manufacturing Same,” US Patent No. 5234856, Aug. 10,1993.
10. Lee et al., “Method of Manufacturing a Semiconductor Device with Vertically Stacked Structure,” US Patent No. 5236858 Aug. 17, 1993.
11. K. Gulati et. al., “Single Event Mirroring and DRAM Sense Amplifier Designs for Improved Single-Event-Upset Performance,” in this issue of the IEEE Transactions of Nuclear Science.
12. L.W. Massengill, “SEU Modeling and Prediction techniques,” 1993 Nuclear and Space Radiation Effect Conference Short Course.