Transistor sizing for radiation hardening

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 310-315

  Zhou, Quming ^a   Mohanram, Kartik ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; COMPUTER AIDED DESIGN; HARDENING; LOGIC CIRCUITS; LOGIC DESIGN; SPICE;

CMOS GATE; DESIGN-AUTOMATION TOOLS; FAST ANALYSIS; SINGLE EVENT UPSETS; SPICE SIMULATIONS; TRANSISTOR SIZE; TRANSISTOR SIZING;

RADIATION HARDENING;

EID: 84932139590     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315343     Document Type: Conference Paper

References (10)

1. N. Cohen, et al., "Soft Error Considerations for Deep-Submicron CMOS Circuit Applications," Intl. Electron Devices Meeting Technical Digest, pp. 315-318, 1999.
2. P. Dahlgren and P. liden, "A Switch-level Algorithm for Simulation of Transients in Combinational Logic," Proc. Intl. Sym. on Fault-Toleran Computing, pp. 207-216, 1995.
3. A. Dharchoudhury, et al, "Fast Timing Simulation of Transient Fault in Digital Circuits," Proc. Intl. Conf. on Computer-Aided Design, pp. 719-726, 1994.
4. A. I. Kayssi, et al, "Analtical Transient Response of CMOS Inverters," IEEE Trans, on Circuits and Systems, Vol. 39, pp. 42-45, Jan. 1992.
5. G. C. Messenger, "Collection of Charge on Junction Nodes from Ion Tracks," IEEE Trans. on Nuclear Science, Vol. NS-29, pp. 2024-2031, Dec. 1982.
6. K. Mohanram and N. A. Touba, "Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits," Proc. Intl. Test Conference, pp. 893-901, 2003.
7. [MOSIS] http://www.mosis.org
8. S. Nakamura, Applied Numerical Methods in C, Prentice Hall, 1993.
9. Y. H. Shih and S. M. Kang, "Analytic Transient Solution of General MOS Circuit Primitives," IEEE Trans, on Computer-Aided Design, Vol. 11, pp. 719-731, Jun. 1992.
10. P. Shivakumar, et al., "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic," Proc. Intl. Conference on Dependable Systems and Networks, pp. 389-398, 2002.