Fast timing simulation of transient faults in digital circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 719-722

  Dharchoudhury, A ^a   Kang, S M ^a   Cha, H ^a   Patel, J H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIFFERENTIAL EQUATIONS; FAILURE ANALYSIS; LOGIC GATES; MOS DEVICES; MOSFET DEVICES;

BENCHMARK CIRCUITS; PIECEWISE QUADRATIC INJECTED CURRENT WAVEFORM; SINGLE EVENT UPSETS; TIMING LEVEL SIMULATOR; TRANSIENT FAULT SIMULATION;

DIGITAL CIRCUITS;

EID: 0028722343     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)