A novel, highly SEU tolerant digital circuit design approach

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 14-20

  Garg, Rajesh ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT LEVELS; CMOS GATES; CRITICAL CHARGES; DELAY PENALTIES; DIGITAL CIRCUIT DESIGNS; DIGITAL DESIGNS; FAN OUTS; LAYOUT AREAS; LOW PROBABILITIES; NMOS DEVICES; NMOS TRANSISTORS; OUTPUT VALUES; PMOS TRANSISTORS; RADIATION PARTICLES; RADIATION TOLERANT; RADIATION-HARDENED; SEU TOLERANCES; SOFT ERROR RATES; SOFT ERRORS; STANDARD CELLS;

DESIGN; DIGITAL INTEGRATED CIRCUITS; DIGITAL LIBRARIES; ELECTRIC BATTERIES; ELECTRIC NETWORK ANALYSIS; HARDENING; INTEGRATED CIRCUIT MANUFACTURE; RADIATION HARDENING; TRANSISTORS; URANIUM POWDER METALLURGY;

RADIATION;

EID: 78650420917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751834     Document Type: Conference Paper

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