Genetic algorithm-based FSM synthesis with area-power trade-offs

Integration, the VLSI Journal

Volumn 42, Issue 3, 2009, Pages 376-384

  Chaudhury, Saurabh ^a   Sistla, Krishna Teja ^b   Chattopadhyay, Santanu ^c  

^a NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR   (India)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Area power trade offs; FSM synthesis; Genetic algorithm; Low leakage

Indexed keywords

AREA REQUIREMENTS; AREA-POWER TRADE-OFFS; ASSIGNMENT TECHNIQUES; DESIGN PARAMETERS; DYNAMIC CMOS; DYNAMIC POWER; DYNAMIC POWER CONSUMPTION; ENCODING STRATEGIES; FINITE-STATE MACHINES; FSM SYNTHESIS; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; LOW LEAKAGE; POWER DENSITIES; SCALING DOWNS; STATE ENCODING; STATIC POWER;

COMMERCE; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); GENETIC ALGORITHMS; STATE ASSIGNMENT;

LEAKAGE CURRENTS;

EID: 67349275031     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2008.11.005     Document Type: Article

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