GALLOP: Genetic algorithm based low power FSM synthesis by simultaneous partitioning and state assignment

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 533-538

  Venkataraman, Ganesh ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^b  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Automata; Circuit synthesis; Cities and towns; Cost function; Encoding; Flip flops; Genetic algorithms; Minimization; Power dissipation; Sequential circuits

Indexed keywords

ALGORITHMS; COST FUNCTIONS; DESIGN; EMBEDDED SOFTWARE; ENCODING (SYMBOLS); ENERGY DISSIPATION; FLIP FLOP CIRCUITS; GENETIC ALGORITHMS; LOGIC CIRCUITS; OPTIMIZATION; SEQUENTIAL CIRCUITS; STATE ASSIGNMENT; SYSTEMS ANALYSIS; VLSI CIRCUITS;

AUTOMATA; CIRCUIT SYNTHESIS; CITIES AND TOWNS; LOW POWER; POWER REDUCTIONS;

EMBEDDED SYSTEMS;

EID: 84941358530     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183189     Document Type: Conference Paper

References (15)

1. K. Keutzer and P. Vanbekbergen, "The Impact of CAD on the design of low power digital circuits", Dig. of Papers, IEEE Symp., pp. 42-45, 1994
2. T. Villa and A. Sangiovinni-Vincentilli, "NOVA: State Assignment of finite state machines for optimal two-level logic implementation", IEEE Trans. on CAD, pp.905-924, Sept 1990
3. S. Devadas, H-K. T. Ma, A. R. Newton, and Sangiovinni Vincentilli, "MUSTANG: State Assignment of finite state machines targeting multi-level implementations", IEEE Trans. on CAD, pp.1290-1300, Dec. 1988
4. Chi-Ying Tsui, Massoud Pedram and Alvin Despain, "Low-Power State Assignment Targeting Two and Multilevel Implementations", IEEE Trans. on CAD, pp. 1281-1291, Dec. 1998
5. S. Chattopadhyay, "Low power state assignment and flipflop selection for finite state machine synthesis -a genetic algorithmic approach", IEE Proceedings, pp. 147-151, July-Sept. 2001
6. Jose C. Monteiro and Arlindo L. Oliveira, "FSM decomposition by direct circuit manipulation applied to low power design", ASP-DAC 2000, pp:351-358
7. Luca Benini, Giovanni De Micheli and Frederik Vermulen, "Finite State Machine Partitioning for Low Power", ISCAS 98, pp:5-8
8. Wai-Kwong Lee and Chi-Ying Tsui, "Finite State Machine Partitioning for Low Power", ISCAS 99, pp: 306-309
9. Sue-Hing Chow, Yi-Cheng Ho and Tingting Hwang, "Low Power Realization of Finite State Machines-A Decomposition Approach", ACM Trans. on Design Automation of Electronic Systems, pp. 315-340, July 1996
10. Luca Benini and Giovanni De Micheli, "Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines", IEEE Trans. on CAD, pp. 630-643, June 1996
11. D. Goldberg, "Genetic Algorithms in search, optimization and machine learning", Addison-Welsey, 1989
12. Pinaki Mazumder and Elizabeth M. Rudnick, "Genetic Algorithms in VLSI Design, Layout and Test Automation", Prentice Hall PTR, 1999
13. Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai and Kun-Lin Tsai, "A Bipolar-Codec Architecture to reduce Power in Pipelined Circuits", IEEE Trans. on CAD, pp:343-348, Feb 2001.
14. A. E. A Almaini, J. F. Miller, P. Thomson and S. Billina, "State Assignment of finite state machines using a genetic algorithm", Computers and Digital Techniques, IEE Proceedings, pp. 279-286, July 1995
15. E. Sentovich, K. Singh, et. al. "SIS: a system for sequential circuit synthesis", Tech. Rep. M92/41, Electronic Research Laboratory, College of Engineering, University of California, Berkeley, 1992.