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Volumn , Issue , 2000, Pages 351-358

FSM decomposition by direct circuit manipulation applied to low power design

Author keywords

[No Author keywords available]

Indexed keywords

DIRECT MANIPULATION; EXPLICIT TECHNIQUES; FSM DECOMPOSITION; LOW-POWER DESIGN; POWER REDUCTIONS; SEQUENTIAL LOGIC CIRCUITS; STATE TRANSITION GRAPHS; SWITCHING ACTIVITIES;

EID: 0348183361     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368678     Document Type: Conference Paper
Times cited : (11)

References (17)
  • 8
    • 3042842796 scopus 로고
    • Symbolic Analysis of a Decomposition of Information Processing
    • June
    • J. Hartmanis. Symbolic Analysis of a Decomposition of Information Processing. Information Control, 3:154-178, June 1960.
    • (1960) Information Control , vol.3 , pp. 154-178
    • Hartmanis, J.1
  • 9
    • 84990479742 scopus 로고
    • An Efficient Heuristic Procedure for Partitioning Graphs
    • February
    • B. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning Graphs. The Bell System Technical Journal, pages 291-307, February 1970.
    • (1970) The Bell System Technical Journal , pp. 291-307
    • Kernighan, B.1    Lin, S.2
  • 11
    • 0028711580 scopus 로고
    • A Survey of Power Estimation Techniques in VLSI Circuits
    • (Invited Paper). December
    • F. Najm. A Survey of Power Estimation Techniques in VLSI Circuits (Invited Paper). IEEE Transactions on VLSI Systems, 2(4):446-455, December 1994.
    • (1994) IEEE Transactions on VLSI Systems , vol.2 , Issue.4 , pp. 446-455
    • Najm, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.