ILP-based optimization of sequential circuits for low power

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 140-145

  Gao, Feng ^a   Hayes, J P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Algorithm design and analysis; Encoding; Energy consumption; Integer linear programming; Logic; Minimization; Permission; Power dissipation; Power generation; Sequential circuits

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); ENERGY DISSIPATION; ENERGY UTILIZATION; INDUCTIVE LOGIC PROGRAMMING (ILP); INTEGER PROGRAMMING; LOGIC CIRCUITS; OPTIMIZATION; POWER ELECTRONICS; POWER GENERATION; SEQUENTIAL CIRCUITS;

ALGORITHM DESIGN AND ANALYSIS; CONVENTIONAL CIRCUITS; ILP-BASED OPTIMIZATION; INTEGER LINEAR PROGRAMMING; LOGIC; PERMISSION; POWER MINIMIZATION; STATE ENCODING;

LOW POWER ELECTRONICS;

EID: 1542329245     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231850     Document Type: Conference Paper

References (17)

1. L. Benini, G. De Micheli, and F. Vermulen, "Finite State Machine Partitioning for Low Power", Proc. International Symposium on Circuits and Systems, 1998, pp. 5-8.
2. S. H. Chow, Y. C. Ho, T. Hwang and C. L. Liu, "Low Power Realization of Finite State Machines-A Decomposition Approach", ACM TODAES, vol. 1, 1996, pp. 315-340.
3. Collaborative Benchmarking Lab., North Carolina State Univ., http://www.cbl.ncsu.edu/benchmarks.
4. S. Devadas, et al., "MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations", IEEE Trans. on CAD, vol. 7, 1988, pp. 1290-1300.
5. ILOG cplex webpage. http://www.ilog.com/products/cplex/.
6. H. R. Lewis and C. H. Papadimitriou, Elements of the Theory of Computation, Englewood Cliffs, NJ: Prentice-Hall, 1981.
7. E. Macii, M. Pedram, and F. Somenzi, "High-Level Power Modeling, Estimation, and Optimization", IEEE Trans. on CAD, vol. 17, 1998, pp. 1061-1079.
8. J. C. Monterio and A. L. Oliveria, "Finite State Machine Decomposition for Low Power", Proc. Design Automaton Conference, 1998, pp. 758-763.
9. J. C. Monterio and A. L. Oliveria, "FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design", Proc. Asia South Pacific Design Automation Conference, 2000, pp. 351-358.
10. E. Olson and S. Kang, "Low-Power State Assignment for Finite State Machines", Proc. International Symposium on Low Power Design, 1994, pp. 63-68.
11. nd Edition, New York: McGraw-Hill, 1984.
12. M. Pedram, "Power Minimization in IC Design: Principles and Application", ACM TODAES, vol. 1, 1996, pp. 3-56.
13. K. Roy and S. Prasad, "Circuit Activity Based Logic Synthesis for Low Power Reliable Operations", IEEE Trans. on VLSI, vol. 1, 1993, pp. 503-513.
14. E. Sentovich, et al., "Sequential Circuit Design Using Synthesis and Optimization", Proc. International Conference on CAD, 1992, pp. 328-333.
15. Synopsys, Design Analyzer data sheet, http://www.synopsys.com/products/logic/design-compiler.html.
16. C. Y. Tsui, M. Pedram, and A. Despain, "Low-Power State Assignment Targeting Two and Multilevel Implementations", IEEE Trans. on CAD, vol. 17, 1998, pp. 1281-1291.
17. T. Villa and A. Sangiovanni-Vincentelli, "NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementation", IEEE Trans. on CAD, vol. 9, 1990, pp. 905-924.