Low power state assignment and flipflop selection for finite state machine synthesis-a genetic algorithmic approach

IEE Proceedings: Computers and Digital Techniques

Volumn 148, Issue 4-5, 2001, Pages 147-151

  Chattopadhyay, S ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CONVERGENCE OF NUMERICAL METHODS; FLIP FLOP CIRCUITS; GENETIC ALGORITHMS; LOGIC DESIGN;

FINITE STATE MACHINE; MULTIPROCESSOR ENVIRONMENT;

FINITE AUTOMATA;

EID: 0035385511     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20010666     Document Type: Article

References (14)

1. NOVA: State assignment of finite state machines for optimal two-level logic implementation
2. Mustang: State assignment of finite state machines for optimal-multi level logic implementations
3. Synthesis of multiple level logic from symbolic high-level description languages
4. Syclop: Synthesis of CMOS logic for low power applications
5. Low-power state assignment for finite state machines search
6. State assignment for low power dissipation
7. Reencoding sequential circuits to reduce power dissipation
8. A symbolic algorithm for low-power sequential synthesis
9. Low power state assignment targeting two- and multi-level logic implementations
10. SIS: A system for sequential circuit synthesis
11. Adaptation in natural and artificial systems
12. Designing genetic algorithms for the state assignment problem
13. Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machine synthesis
14. Computer-aided design techniques for low power sequential logic circuits