FSM Re-engineering and its application in low power state encoding

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 254-259

  Yuan, Lin ^a   Qu, Gang ^a   Villa, Tiziano ^b,c   Sangiovanni Vincentelli, Alberto ^b,d  

^a UNIVERSITY OF MARYLAND   (United States)

^b PARADES   (Italy)

^c UNIVERSITY OF UDINE   (Italy)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ENCODING (SYMBOLS); GENETIC ALGORITHMS; REENGINEERING; SIGNAL ENCODING; SPACE RESEARCH; STATE ASSIGNMENT;

INTEGER LINEAR PROGRAMMING FORMULATION; ITS APPLICATIONS; OPTIMIZATION PROCEDURES; PERFORMANCE ENHANCEMENTS; SOLUTION SPACE EXPLORATION; SWITCHING ACTIVITIES; SWITCHING ACTIVITY REDUCTION; SYNTHESIS SOLUTION;

INTEGER PROGRAMMING;

EID: 84861419625     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120844     Document Type: Conference Paper

References (10)

1. L. Benini and G- D. Micheli, "State Assignment for Low Power Dissipation," IEEE Journal of Solid-State Circuits, Vol.30, pp.258-268, Mar. 1995.
2. G. D. Hachtel, et al., "Re-Encoding Sequential Circuits to Reduce Power Dissipation," International Workshop on Low-Power Design, Apr, 1994. pp. 272-282, 1974.
3. I. Lentberski, M. Koegst, S. Cotofana, and B. Juurlink, "FSM Non-Minimal Slate Encoding for Low Power," Proceedings of the 23rd International Conference on Microelectronics, Yugoslavia, May 2002.
4. W. Noth, and R. Kolla, "Spanning Tree Based State Encoding for Low Power dissipation," Proceedings of DATE, pp. 168, Mar. 1999
5. E. Olson and S.M.Kang, "State assignment for low-power FSM synthesis using genetic local search," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 140-143, CA, May 1994.
6. K. Roy and S. C. Prasad, "SYCLOP: Synthesis of CMOS logic for low power application," Proceedings of ICCAD, pp. 464-467, Oct. 1992.
7. E. Sentovich, et al., "SIS: A System for Sequential Circuit Synthesis," Electronics Research Laboratory' Memorandum, U.CBerkeley
8. C. Tsui, M. Pedram, C. Chen, and A. M. Despain, "Low Power State Assignment Targeting Two- and Multi-level Logic Implementations," Proceedings of ICCAD, pp. 82-87, CA, 1994.
9. V. Veeramachaneni, A. Tyagi, and S. Rajgopal,."Re-encoding for Low Power State Assignment of FSMs," Proceedings of ISLPED, pp. 173178, Apr. 1995.
10. S. Washabaugh, P. Franzon, and H. Nagle, "SABSA: Switching Activity Based State Assignment," IEEE Solid State Circuits and Technology Committee Workshop on Low Power Electronics, 1993.