Near void-free assembly development of flip chip using no-flow underfill

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 32, Issue 2, 2009, Pages 106-114

  Lee, Sangil ^a   Yim, Myung J ^b   Master, Raj N ^c   Wong, C P ^b   Baldwin, Daniel F ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

Assembly yield; Fine pitch; Flip chip; High I O density; No flow underfill; Reliability; Void formation

Indexed keywords

ASSEMBLY YIELD; FINE PITCH; FLIP CHIP; HIGH I/O DENSITY; NO-FLOW UNDERFILL; VOID FORMATION;

ASSEMBLY; DESIGN OF EXPERIMENTS; RELIABILITY;

FLIP CHIP DEVICES;

EID: 67349245930     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2009.2015592     Document Type: Article

References (26)

1. D. Milner, C. Paydenkar, and D. F. Baldwin, "Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials," IEEE Trans. Electron. Packag. Manuf., vol. 25, no. 2, pp. 107-112, Apr. 2002.
2. J. Giesler, G. O. Malley, M. Williams, and S. Machuga, "Flip chip on board connection technology: Process characterization and reliability," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 36, no. 3, pp. 449-450, Aug. 1996.
3. D. W. Milner, "Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials," IEEE Trans. Electron. Packag. Manuf. vol. 24, no. 4, pp. 307-312, Oct. 2001.
4. S. Lee, R. Master, and D. Baldwin, "Assembly yields characterization of high I/O density, fine pitch flip chip in package using no-flow underfill," in Proc. Electron. Compon. Technol. Conf., 2007, pp. 35-41.
5. S. Lee, R. Master, and D. Baldwin, "Assembly yields characterization and failure analysis of flip chip in package using no-flow underfill," in Proc. Int. Wafer Level Packag. Congr., 2007, pp. 169-175.
6. C. S. Hau-Riege, S. P. Hau-Riege, and A. P. Marathe, "The effect of interlevel dielectric on the critical tensile stress to void nucleation for the reliability of Cu interconnects," in J. Appl. Phys., Nov. 15, 2004, vol. 96, pp. 5792-5796.
7. S. Lee, R. Master, and D. Baldwin, "Void formation study of high I/O density, fine pitch flip chip in package using no-flow underfill," Surface Mount Technol. Assoc. Int., pp. 525-530, 2007.
8. S. F. Popelar, "A parametric study of flip chip reliability based on solder fatigue modeling," in Proc. IEEE/CPMT Int. Electron. Manuf. Technol. Symp., 1997, pp. 299-307.
9. T.-M. Niu, "Void-effect modeling of flip-chip encapsulation on ceramic substrate," IEEE Trans. Compon. Packag. Technol., vol. 22, no. 4, pp. 484-487, Dec. 1999.
10. M. Yunus, K. Srihari, J. M. Pitarresi, and A. Primavera, "Effect of voids on the reliability of BGA/CSP solder joints," Microelectron. Rel., vol. 43, pp. 2077-2086, 2003.
11. D. Wang and R. L. Panton, "Experimental study of void formation in eutectic and lead-free solder bumps of flip-chip assemblies," J. Electron. Packag., vol. 128, pp. 202-207, 2006.
12. M. Colella and D. F. Baldwin, "Near void free hybrid no-flow underfill flip chip process technology," in Proc. Electron. Compon. Technol. Conf., 2004, vol. 1, pp. 780-788.
13. S. Lee, M. J. Yim, R. Master, C. P. Wong, and D. F. Baldwin, "Void formation study of flip chip in package using no-flow underfill," IEEE Trans. Electron. Packag. Manuf., vol. 31, no. 4, pp. 297-305, Dec. 2007.
14. L. Goenka and A. Achari, "Void formation in flip chip solder bumps - Part 2," in Proc. IEEE CPMT Int. Electron. Manuf. Technol. Symp., 1996, pp. 430-437.
15. L. Goenka and A. Achari, "Void formation in flip chip solder bumps - Part1," in Proc. IEEE CPMT Int. Electron. Manuf. Technol. Symp., 1995, pp. 14-19.
16. S. W. Liang, Y. W. Chang, T. L. Shao, and C. Chen, "Effect of three-dimensional current and temperature distributions on void formation and propagation in flip-chip solder joints during electromigration," Appl. Phys. Lett., vol. 89, 2006, 22117.
17. D. Wang and R. L. Panton, "Experimental study of void formation in high-lead solder joints of flip-chip assemblies," Trans. ASME, vol. 127, pp. 120-126, 2005.
18. D. Wang and R. L. Panton, "Effect of reversing heat flux direction during reflow on void formation in high-lead solder bumps," Trans. ASME, vol. 127, pp. 440-445, 2005.
19. J. M. Hurley, T. Berfield, S. Ye, R. W. Johnson, R. Zhao, and G. Tian, "Kinetic modeling of no-flow underfill cure and its relationship to solder wetting and voiding," in Proc. Electron. Compon. Technol. Conf., 2002, pp. 828-833.
20. T. Wang, T. H. Chew, C. Lum, Y. X. Chew, P. Miao, and L. Foo, "Assessment of flip chip assembly and reliability via reflowable underfill," in Proc. Electron. Compon. Technol. Conf., 2001, pp. 803-809.
21. T. Lazarakis, "Processing of no-flow fluxing underfills for flip chip assembly," in Proc. Int. Adv. Packag. Mater. Symp., 2002, pp. 232-237.
22. M. Colella, "Evaluation, optimization, and reliability of no-flow underfill process," in Mechanical Engineering. Atlanta, GA: Georgia Inst. Technol., 2004, vol. Master.
23. M. Colella and D. Baldwin, "Void free processing of flip chip on board assemblies using no-flow underfills," Proc. IEEE Adv. Packag. Mater. pp. 272-281-, 2004.
24. S. Lee, M. J. Yim, R. Master, C. P. Wong, and D. F. Baldwin, "Void formation study of flip chip in package using no-flow underfill," IEEE Trans. Electron. Packag. Manuf., vol. 31, no. 4, pp. 297-305, Oct. 2008.
25. "Compendium of Chemical Terminology," IUPAC, 1987.
26. S. Lee, M. J. Yim, R. Master, C. P. Wong, and D. F. Baldwin, "Assembly yield characterization and void formation study on high I/O density and fine pitch flip chip in package using no-flow underfill," Surface Mount Technol. Assoc. Int., pp. 673-680, 2008.