Experimental study of void formation in eutectic and lead-free solder bumps of flip-chip assemblies

Journal of Electronic Packaging

Volumn 128, Issue 3, 2006, Pages 202-207

  Wang, Daijiao ^b   Panton, Ronald L ^a,b  

^a ASME   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EUTECTICS; HEAT FLUX; LEAD; LOGIC DESIGN; SOLDERED JOINTS; TEMPERATURE DISTRIBUTION;

FLIP-CHIP ASSEMBLIES; HEAT FLUX DIRECTIONS; THERMOCAPILLARY THEORY; VOID FORMATION;

FLIP CHIP DEVICES;

EID: 33750365225     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.2229215     Document Type: Review

References (9)

1. Lau, J. H., and Pao, Y.-H., 1997, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill New York, Chap. 6.
2. Wang, D., and Panton, R. L., 2005, "Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies," ASME J. Electron. Packag., 127(2), pp. 120-126.
3. Wang, D., and Panton, R. L., 2005, "Effect of Reversing Heat Flux Direction during Reflow on Void Formation in High-Lead Solder Bumps," ASME J. Electron. Packag., 127(4), pp. 440-445.
4. Chiu, C. S., and Lee, N. C., 1997, "Voiding in BGA at Solder Bumping Stage," ISHM Proceedings of Microelectronics and Packaging Conference, Philadelphia, PA, pp. 462-471.
5. Chan, Y. C., Xie, D. J., and Lai, J. K. L., 1995, "Characteristics of Porosity in Solder Pastes during Infrared Reflow Soldering," J. Mater. Sci., 30(21), pp. 5543-5550.
6. Goenka, L., and Achari, A., 1995, "Void Formation in Flip-Chip Solder Bumps - Part I," Proceeding of the 18th IEEE/CPMT Symposium, Austin, TX, pp. 14-19.
7. Bailey, C., Lu, H., and Wheeler, D., 2002, "Computational Modeling Techniques for Reliability of Electronic Components on Printed Circuit Boards," Appl. Numer. Math., 40, pp. 101-117.
8. Goenka, L., and Achari, A., 1996, "Void Formation in Flip Chip Solder Bumps - Part II," Proceeding of the 19th IEEE/CPMT Symposium, Austin, TX, pp. 430-437.
9. Panton, R. L., Lee, J. W., Goenka, L., and Achari, A., 2003, "Simulation of Void Growth in Molten Solder Bumps," ASME J. Electron. Packag., 125(3), pp. 329-334.