Assembly yields characterization of high IO density, fine pitch flip chip in package using no-flow underfill

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 35-41

  Lee, Sangil ^a   Baldwin, Daniel F ^a   Master, Raj ^b   Parthasarathy, Srinivasan ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SIZE; FLOW UNDERFILLS;

ELECTRONICS PACKAGING; NUMERICAL METHODS; PARAMETER ESTIMATION; SENSITIVITY ANALYSIS;

FLIP CHIP DEVICES;

EID: 35348855690     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373773     Document Type: Conference Paper

References (6)

1. John H. Lau, Flip Chip Technologies, McGraw-Hill, 1996:.
2. Darbha Suryanarayana, et al., "Enhancement of Flip- Chip Fatigue Life by Encapsulation", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 14,No. 1, March 1991
3. Ryan Thorpe and Daniel Baldwin Ph.D., "High Throughput Flip Chip Processing and Reliability Analysis Using NoFlow Underfills", Electronic Components and Technology Conference, 1999
4. David W. Milner, "High Throughput Flip Chip Assembly Process Application and Assessment Using No-Flow Underfill Materials", M.A. Thesis, 2001
5. Michael Colella and Daniel F. Baldwin, "Process Development: A Void Free Hybrid No-Flow Underfill Process", Electronics Components and Technology Conference, 2004
6. Ryan Thorpe, Daniel F. Baldwin, Brian Smith, and Lawrence McGovern, "Yield Analysis and Process Modeling of Low Cost, High Throughput Flip Chip Assembly Based on No-Flow Underfills" IEEE Transactions on Electronics Packaging Manufacturing, Vol. 24, No. 2, April 2001