Near void free hybrid no-flow underfill flip chip process technology

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 780-788

  Colella, Michael ^a   Baldwin, Daniel ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Area array; Electronics packaging; Flip chip; No flow underfill; Process optimization; Void free

Indexed keywords

AREA ARRAY; NO-FLOW UNDERFILL; PROCESS OPTIMIZATION; VOID FREE;

CAPILLARY FLOW; ELECTRONICS PACKAGING; RELIABILITY; SUBSTRATES; THERMAL CYCLING; THERMAL EXPANSION;

FLIP CHIP DEVICES;

EID: 10444268035     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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3. D. Gamota and C. Melton, "Reflowable material systems to integrate the reflow and encapsulant dispensing process for flip chip on board assemblies", Proc. Int. Conf. Electron. Assem. Mater., Atlanta, GA, 1996.
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5. Ryan Thorpe, Daniel F. Baldwin, Brian Smith, and Lawrence McGovern, "Yield Analysis and Process Modeling of Low Cost, High Throughput Flip Chip Assembly Based on No-Flow Underfills" IEEE Transactions on Electronics Packaging Manufacturing, Vol. 24, No. 2, April 2001
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9. Theodores Lazarakis, "Processing of no-flow fluxing underfills for flip chip assembly" MSME Thesis, School of Mechanical Engineering, Georgia Tech, Atlanta, GA, 2002
10. Pascarella, N., "Compression Flow Modeling of Underfill Encapsulants for Low Cost Flip Chip Assembly'", IEEE Transactions on Components, Packaging, and Manufacturing technology, Vol. 21, No. 4, 1998
11. nd Electronics Packaging Technology Conference, 1998, pp 264-8
12. Michael Colella "Evaluation, optimization, and reliability, of no-flow underfill process" MSME Thesis, School of Mechanical Engineering, Georgia Tech, Atlanta, GA, 2004