Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 24, Issue 4, 2001, Pages 307-312

  Milner, David ^b   Baldwin, Daniel F ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

High lead solder bumps; Underfill; Void capture; Void formation

Indexed keywords

EUTECTIC SOLDER WETTING;

ELECTRONICS PACKAGING; EUTECTICS; LAMINATES; SOLDERING; SUBSTRATES; SURFACE MOUNT TECHNOLOGY; WETTING;

FLIP CHIP DEVICES;

EID: 0035493793     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/6104.980040     Document Type: Article

References (12)

1. Manufacturability issues in flip chip on laminate assembly
2. Advanced encapsulation processing for low cost flip chip assembly - A cost analysis
3. Advanced encapsulation processing for low cost flip chip assembly - A cost analysis
4. Thermal process optimization and monitoring
5. Failure mode analysis of advanced electronics packaging