Low-cost CP-PLL DFT structure implementation for digital testing application

IEEE Transactions on Instrumentation and Measurement

Volumn 58, Issue 6, 2009, Pages 1897-1906

  Hsu, Chun Lung ^a   Lai, Yi Ting ^a  

^a NATIONAL DONG HWA UNIVERSITY   (Taiwan)

Author keywords

Area overhead; Charge pump phase locked loop (CP PLL); Design for testability (DFT); Digital testing; Fault coverage

Indexed keywords

AREA OVERHEAD; CHARGE-PUMP PHASE-LOCKED LOOP (CP-PLL); DESIGN FOR TESTABILITY (DFT); DIGITAL TESTING; FAULT COVERAGE;

DELAY CIRCUITS; DESIGN FOR TESTABILITY; INSTRUMENT TESTING; OSCILLATORS (ELECTRONIC); PROBABILITY DENSITY FUNCTION; PUMPS; SPURIOUS SIGNAL NOISE;

PHASE LOCKED LOOPS;

EID: 67349227433     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2008.2005852     Document Type: Conference Paper

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