DFT for delay fault testing of high-performance digital circuits

IEEE Design and Test of Computers

Volumn 21, Issue 3, 2004, Pages 248-258

  Chatterjee, Bhaskar ^a   Sachdev, Manoj ^a   Keshavarzi, Ali ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; FAILURE ANALYSIS; LEAKAGE CURRENTS; LOGIC GATES; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CIRCUIT UNDER TEST; DELAY FAULT TESTING; DOMINO LOGIC GATE; FOOTER TRANSISTOR;

DESIGN FOR TESTABILITY;

EID: 3042585556     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.10     Document Type: Article

References (11)

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